A High-Speed and Energy-Efficient Compressor-Technique based 4-bit Signed Multiply Accumulate (MAC) Unit

Abstract

This work presents the design of a novel 2-stage pipelined 4-bit signed Multiply and Accumulate (MAC) unit (called 2s4BSMAC), which is low-power, high-speed, and high-throughput. The unit incorporates a unique compressor-based 4-bit Vedic Signed Multiplier (VSM) architecture, a compressor-based 16-bit Ripple Carry Adder (RCA) architecture, and a saturation unit. Without adding buffers at intermediate stages, the proposed 4-bit Vedic Signed Multiplier (VSM) and 16-bit Ripple Carry Adder (RCA) based on compressors overcome the driving limitation of transmission gates. This paper introduces a novel hybrid Full Adder (FTGHFA-21T), low-power and high-speed, utilizing FinFET-Transmission Gate technology and 21 transistors. The FTGHFA-21T adder, operating at nominal supply voltage, exhibited significant improvements in maximum propagation delay of 39.02%, average power consumption of 13.4%, and Power Delay Product (PDP) of 47.18% as compared to the Transmission Gate Adder (TGA). The PVT analysis is conducted to analyze and comprehend the circuit's variability in response to environmental and fabrication variations. The proposed compressor-based 16-bit RCA and the proposed compressor-based 4-bit VSM utilizing the FTGHFA-21T adder shows 5.41% and 11.92% reduction in PDP compared to the proposed compressor-based 16-bit RCA and the proposed compressor-based 4-bit VSM utilizing the TGA respectively. At the nominal supply voltage, the proposed 2s4BSMAC unit using the suggested adder exhibits a 7.14% enhancement in PDP and a 7.22% increase in throughput compared to the TGA-based design. The simulation uses 18nm Fin Field Effect Transistor (FinFET) technology in the Cadence Virtuoso tool at the nominal supply voltage of 0.8V with a nominal temperature of 27°C.